1. Field of the Invention
This invention relates to a method for manufacturing semiconductor integrated circuits and more particularly, to a method for isolating elements of a semiconductor integrated circuit from each other.
2. Description of the Prior Art
In the manufacture of metal-oxide-semiconductor large scale integrated (MOSLSI) circuits, the dielectric isolation between the elements of such circuit without producing any so-called bird beaks is typically effected by the procedure particularly shown in FIGS. 1(a) through 1(d). That is, on a p-type substrate 1 are formed, for example, a 0.05 micron thick SiO.sub.2 film 2 and a 0.1 micron thick Si.sub.3 N.sub.4 film 3. Then, the Si.sub.3 N.sub.4 film 3 and SiO.sub.2 film 2 on the isolation region are etched through a photoresist film 4 by the photo-etching technique, followed by anisotropically etching the Si substrate 1 to form a groove 5 with a depth of about 0.5 microns. The ion injection such as of boron for channel stopper is carried out to form an ion-injected region 6 at the bottom of the groove 5 (FIG. 1(a)).
The photoresist film 4 is then removed, after which an about 0.02 micron thick SiO.sub.2 film 7 is formed on the exposed surface of the groove 5 by the thermal oxidation method, on which is further formed a 0.1 micron thick Si.sub.3 N.sub.4 film by the CVD method. This Si.sub.3 N.sub.4 film 8 is then etched by a sputter-etching or ion-etching technique so that the film 8 remains only at opposite sides of the groove 5 (FIG. 1(b)).
Upon oxidation in pressurized steam of 6-10 kg/m.sup.2, the oxidation proceeds only from the bottom of the groove 5 to form a 1 micron thick isolation SiO.sub.2 film 9 in the groove 5. At the same time, the boron in the ion-injected region 6 serves as the diffusion source and a p.sup.+ -type channel stopper region 11 is formed as shown in FIG. 1(c). The oxidation is continued until the SiO.sub.2 film 9 grows to such a level of about the surface of the substrate 1. In this connection, because of the formation of the Si.sub.3 N.sub.4 film 9 along the sides of the groove 5, the oxidation does not proceed towards the sides of the groove. As a consequence, the SiO.sub.2 isolation film 9 becomes thinner in portions brought into contact with the Si.sub.3 N.sub.4 film to form a gap 10. The formation of this gap causes the problem of worsening the yield of the resulting fine pattern.
When the substrate on which the Si.sub.3 N.sub.4 film 3 is formed is subjected to the oxidation over a long period in order to form the SiO.sub.2 film 9, a thin Si.sub.3 N.sub.4 film 15 will undesirably be formed in some portions of the Si substrate beneath the SiO.sub.2.
In this condition, the Si.sub.3 N.sub.4 film 3 and the SiO.sub.2 film 2 are removed and a gate oxide film 16, a polycrystalline Si gate electrode 12 and n.sup.+ source-drain regions 13, 14 are formed. In this step, the gate oxide film 16 is not formed on the Si.sub.3 N.sub.4 film regions 15 which have been partly formed on the substrate 1 upon formation of the SiO.sub.2 film 9 (FIG. 1(d)). By this, the occurrence of pinholes in the gate oxide film 16 increases, causing the rate of short-circuit between the polycrystalline electrode 12 and the Si substrate 1 to increase with a decrease in yield of the LSI circuit.
The LSI circuit obtained by these steps has several drawbacks. That is, when the SiO.sub.2 film 9 is formed, only part of the Si substrate exposed at the bottom of the groove 5 contributes to the formation of the SiO.sub.2 film or is consumed. When oxidized, Si is converted into SiO.sub.2 with a thickness of about two times as large as the consumed Si, so that the groove 5 is filled with the growing SiO.sub.2 film 9. Because of the high degree of conversion, the strains established between the SiO.sub.2 film 9 and the Si substrate 1 become great, causing crystal defects around the SiO.sub.2 film 9 to occur with the attendant leakage current between the substrate 1 and the drain-source regions 13, 14. This leads to a lowering in yield of the LSI circuit. Another drawback is that the contact of the p.sup.+ -type channel stopper region 11 with the n.sup.+ -type drain region 14 will lower the reverse voltage and increase the p-n junction capacitance between the substrate and the drain region.